High-radiation environments may be associated with systems ranging from military and aeronautical to commercial and industrial. For example, outer space instrumentation has to operate in high-radiation environments. Depending on a particular mission, the high-radiation environments may include solar and cosmic radiation as well as trapped high energy electron and proton belts in the vicinity of planetary bodies. The inability to replace hardware failures on long-term space instrumentation, such as satellites, necessitates rigorous instrument design and component selection to ensure reliability during the mission timeline. Semiconductor circuits and devices, including complementary metal-oxide-semiconductor (CMOS) devices, are often part of systems and devices used in such harsh environments. However, semiconductors are prone to damage from radiation due to the nature of semiconductors, such as small band gap materials operating with limited numbers of charge carriers.
Radiation damage may include short term effects, which may be either temporary or permanent, or long term effects, which tend to be permanent. Total ionization damage involves impacts of high energy radiation resulting in the creation of electron-hole pairs. In materials with high electron and hole mobilities, electrons and holes may quickly re-combine or be swept away in the presence of electric fields. However, in some materials, such as some materials associated with semiconductor fabrication, the holes may become trapped, which may be problematic. A cumulative measure of the total incident ionizing radiation is the Total Ionizing Dose (TID). Ionizing radiation may impinge on oxides in a semiconductor device and generate electron-hole pairs in the oxides. Electrons tend to be very mobile in an oxide, while holes tend to be very immobile in an oxide, such that the holes may become trapped, which may result in a net positive charge. Mobility differences between electrons and holes in oxides may be several orders of magnitude. In a CMOS circuit, gate oxides may be thin enough so that both electrons and holes may tunnel out and not become trapped; however, isolation oxides are used to isolate areas from one another and must be thick enough to handle voltage differences between different areas. Therefore, holes may remain trapped in isolation oxides, such that ionizing radiation impinging on an isolation oxide may effectively implant a positive charge in the isolation oxide. Electric fields in a CMOS circuit may tend to drive the trapped holes in the isolation oxide down toward an interface between the isolation oxide and a semiconductor substrate, which may interfere with proper operation of the CMOS circuit. The TID may also manifest as increased oxide trapping and other defects.
FIG. 1 shows a three-dimensional view of a two-edge metal-oxide-semiconductor (MOS) transistor 10 formed using a semiconductor substrate 12, according to the prior art. The two-edge MOS transistor 10 includes a source 14, a drain 16, and a gate 18. The source 14 and the drain 16 may be formed in the semiconductor substrate 12 using ion implantation or other semiconductor fabrication techniques. A channel (not shown) is between the source 14 and the drain 16. Isolation oxide 20 surrounds the source 14, the drain 16, and the channel to isolate the two-edge MOS transistor 10 from adjacent devices (not shown). The isolation oxide 20 may be associated with shallow trench isolation (STI). Since the two-edge MOS transistor 10 is fabricated using the semiconductor substrate 12, the semiconductor substrate 12 may have a bulk connection (not shown) electrically connected to the body (not shown) of the two-edge MOS transistor 10. The gate 18 is located over and controls current flow through the channel. A thin layer of gate oxide (not shown) electrically isolates the gate 18 from the channel. The semiconductor substrate 12 may typically be Silicon and the gate 18 may be poly-Silicon, metal, silicide, or alloy that is compatible with semiconductor manufacturing.
The two-edge MOS transistor 10 may be either an N-type MOS (NMOS) transistor or a P-type MOS (PMOS) transistor. In an NMOS transistor, the source 14 and the drain 16 may be N-type semiconductor material, and the body may be P-type semiconductor material. In a PMOS transistor, the source 14 and the drain 16 may be P-type semiconductor material, and the body may be N-type semiconductor material. If the semiconductor substrate 12 is P-type semiconductor material, then the body of an NMOS transistor may be provided by the semiconductor substrate 12 and the body of a PMOS transistor may be provided by an N-well (not shown) in the semiconductor substrate 12. Similarly, if the semiconductor substrate 12 is N-type semiconductor material, then the body of a PMOS transistor may be provided by the semiconductor substrate 12 and the body of an NMOS transistor may be provided by a P-well (not shown) in the semiconductor substrate 12.
FIG. 2 shows three-dimensional details of the two-edge MOS transistor 10 illustrated in FIG. 1. The gate 18 has been omitted to show a channel 22 between the source 14 and the drain 16. The channel 22 has a first edge 24 and a second edge 26 next to the isolation oxide 20. The gate 18 may extend over the first and second edges 24, 26 and the isolation oxide 20, which may be necessary for metallization connections (not shown). In an NMOS transistor, when a voltage at the gate 18 is positive with respect to the source 14, the NMOS transistor may turn on, thereby passing current between the source 14 and the drain 16. Similarly, when the voltage at the gate 18 is equal to or negative with respect to the source 14, the NMOS transistor may turn off, thereby blocking current between the source 14 and the drain 16.
In a high radiation environment, ionizing radiation may impinge on the isolation oxide 20 over time, thereby creating trapped holes and resulting trapped positive charges in the isolation oxide 20. In an NMOS transistor, the trapped positive charges near the first and second edges 24, 26 may behave somewhat like a virtual gate, thereby causing leakage current between the source 14 and the drain 16, lowering a threshold voltage of the two-edge MOS transistor 10, or both. In a PMOS transistor, the trapped positive charges near the first and second edges 24, 26 may behave somewhat like the virtual gate; however, a positive voltage on a PMOS gate relative to a PMOS source further turns off the PMOS transistor. Therefore, the trapped positive charges in particular, and ionizing radiation in general, tend to not be problematic in PMOS devices.
FIG. 3 shows a two-dimensional cross section of a P-type semiconductor substrate 28, which is used to form a first NMOS transistor 30 adjacent to a second NMOS transistor 32. The first NMOS transistor 30 includes a first source 34, a first drain 36, a first gate 38, and first bulk connection material 40. The second NMOS transistor 32 includes a second source 42, a second drain 44, a second gate 46, and second bulk connection material 48. The first and second sources 34, 42 and the first and second drains 36, 44 include N-type semiconductor material. The first and second bulk connection materials 40, 48 may include highly-doped P-type semiconductor material. The first and second gates 38, 46 may include a conductive material, such as poly-Silicon, metal, silicide, or alloy. The first and second gates 38, 46 are electrically isolated from channels between the first source and drain 34, 36 and the second source and drain 42, 44 with a thin gate oxide layer 50.
The first and second NMOS transistors 30, 32 are isolated from each other by the isolation oxide 20; however, the first and second drains 36, 44, which are N-type semiconductor material, and the P-type semiconductor substrate 28 between the first and second drains 36, 44 under the isolation oxide 20 may form a virtual NMOS transistor 52. Even with a voltage difference between the first and second drains 36, 44, the virtual NMOS transistor 52 does not conduct current since there is no gate voltage to bias the virtual NMOS transistor 52 into a conducting state. However, over time in a high radiation environment, ionizing radiation may impinge on the isolation oxide 20, thereby creating trapped holes and resulting trapped positive charges in the isolation oxide 20. These trapped positive charges may function as a positively biased virtual gate for the virtual NMOS transistor 52, thereby causing leakage current to flow between the first and second NMOS transistors 30, 32. Thus, there is a need to reduce or eliminate the effects of ionizing radiation in two-edge NMOS transistors and in adjacent NMOS transistors.